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advance product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. copyright ? cirrus logic, inc. 2006 (all rights reserved) http://www.cirrus.com advance release cs5467 four-channel power/energy ic features ? energy data linearity: 0.1% of reading over 1000:1 dynamic range on-chip functions: - instantaneous voltage, current, and power - i rms and v rms , active, reactive, and apparent power - current fault and voltage sag detect - system calibrations / phase compensation - temperature sensor - energy-to-pulse conversion - positive-only accumulation mode meets accuracy spec for iec, ansi, & jis low power consumption gnd-referenced signals with single supply on-chip, 2.5 v reference power supply monitor simple three-wire digital serial interface ?auto-boot? mode from serial e 2 prom. power supply configurations va+ = +5 v; agnd = 0 v; vd+ = +3.3 v to +5 v description the cs5467 is an integrated power measure- ment device which combines four ? analog-to-digital converters, power calculation engine, energy-to-frequency converter, and a serial interface on a single chip. it is designed to accurately measure instantaneous current and voltage and calculate v rms , i rms , instantaneous power, active power, apparent power, and reac- tive power for high-performance power measurement applications. the cs5467 is optimized to interface to shunt re- sistors or current tr ansformers for current measurement, and to resistive dividers or poten- tial transformers for voltage measurement. the cs5467 also features system-level calibra- tion, a temperature sensor, voltage sag & current fault detection, and phase compensation. ordering in formation: see page 45 . va+ vd+ iin1+ iin1- vin2+ vin2- vrefin vrefout agnd xin xout cpuclk dgnd cs sdo sdi sclk int voltage reference system clock /k clock generator serial interface e-to-f power monitor pfmon x1 reset digital filter calibration mode power calculation engine 4th order ? modulator 2nd order ? modulator temperature sensor digital filter pga hpf option hpf option e1 e2 e3 x10 iin2+ iin2- 4th order ? modulator digital filter pga hpf option vin1+ viin1- digital filter 2nd order ? modulator hpf option x10 mar ?06 ds714a1
cs5467 2 ds714a1 advance release table of contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3. characteristics & s pecifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 analog characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 digital characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4. theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 voltage and current measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 power measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4 linearity performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.1 voltage channel input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.2 current channel inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 iir filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3 high-pass filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4 performing measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.5 energy pulse output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.5.1 active energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.5.2 apparent energy mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5.3 reactive energy m ode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5.4 voltage channel sign mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.5.5 pfmon output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.6 sag and fault dete ct feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.7 on-chip temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.8 voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.9 system initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.10 power-down states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.11 oscillator characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.12 event handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.12.1 typical interrupt handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.13 serial port overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.13.1 serial port interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.14 register paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.15 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6. register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 page 0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 page 1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
cs5467 ds714a1 3 advance release 6.3 page 2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7. system calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1 channel offset and gain calibr ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1.1 calibration sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1.1.1 duration of calibration sequence . . . . . . . . . . . . . . . . . . . . . 39 7.1.2 offset calibration sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1.2.1 dc offset calibration sequence . . . . . . . . . . . . . . . . . . . . . . 39 7.1.2.2 ac offset calibration sequence . . . . . . . . . . . . . . . . . . . . . . 40 7.1.3 gain calibration sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.1.3.1 ac gain calibration sequence . . . . . . . . . . . . . . . . . . . . . . . 40 7.1.3.2 dc gain calibration sequence . . . . . . . . . . . . . . . . . . . . . . . 41 7.1.4 order of calibration seque nces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.2 phase compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.3 active power offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8. auto-boot mode using e 2 prom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.1 auto-boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.2 auto-boot data for e 2 prom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.3 which e 2 proms can be used? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9. basic application ci rcuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10. package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12. environmental, manufacturing, & handling information . . . . . . . . . . . . . . . . . 45 13. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
cs5467 4 ds714a1 advance release list of figures figure 1. cs5464 read and write timing diagrams ................................................................. 12 figure 2. timing diagram for e1 , e2 , and e3 ...................................................................................... 13 figure 3. data measurement flow diagram ............................................................................... 14 figure 4. data measurement flow diagram ............................................................................... 14 figure 5. power calculation flow ............................................................................................... 15 figure 6. active and reactive energy pulse outputs .................................................................. 19 figure 7. apparent energy pulse outputs.................................................................................... 19 figure 8. voltage channel sign pulse outputs ........................................................................... 20 figure 9. pfmon output to pin e3 ........................................................................................................ 20 figure 10. sag and fault detect................................................................................................ .20 figure 11. oscillator connection ............................................................................................... .21 figure 12. cs5467 memory map................................................................................................ 23 figure 13. calibration data flow ............................................................................................... .39 figure 14. system calibration of offset...................................................................................... 39 figure 15. system calibration of gain........................................................................................ 40 figure 16. example of ac gain calibration................................................................................ 40 figure 17. example of ac gain calibration................................................................................ 40 figure 18. typical interface of e 2 prom to cs5467 .................................................................. 42 figure 19. typical connection diagram (single-phase, 3-wire ? direct connect to power line) ...................... 43 list of tables table 1. current channel pga setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 2. e2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3. e3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4. interrupt configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
cs5467 ds714a1 5 advance release 1. overview the cs5467 is a cmos monolithic power measurement device with a computation engine and an ener- gy-to-frequency pulse output. the cs5467 combines four ? analog-to-digital converters (adcs), system calibration, and a computation engine on a single chip. the cs5467 is designed for power measurement applicat ions and is optimized to interface to a cur- rent-sense resistor or transformer for current meas urement, and to a resistive divider or potential trans- former for voltage measurement. the current channels provide programmable gains to accommodate various input levels from a multitude of sensing elements. with a single +5 v supply on va+/agnd, the cs5467?s four input channels can accommodate common mode plus signal levels between (agnd - 0.25 v) and va+. the cs5467 also is equipped with a computati on engine that calculates instantaneous power, i rms , v rms , apparent power, active (real) power, reactive power, and power factor. additional features of the cs5467 include line frequency monitoring, current and volt age sag detection, zero-cross detection, pos- itive-only accumulation mode, and three programmable pulse output pins. to facilitate communication to a microprocessor, the cs5467 includes a simple three- wire serial interface which is spi? and microw- ire? compatible. the cs5467 provides three outputs for energy registration. pins e1 , e2 , and e3 are de- signed to interface to a microprocessor.
cs5467 6 ds714a1 advance release 2. pin description clock generator crystal out crystal in 1,28 xout, xin - the output and input of an inverting amplif ier. oscillation occurs when connected to a crystal, providing an on-chip system clock. alte rnatively, an external clock can be supplied to the xin pin to provide the system clock for the device. cpu clock output 2 cpuclk - output of on-chip oscillator which can drive one standard cmos load. control pins and serial data i/o serial clock input 5 sclk - a schmitt trigger input pin. clocks data fr om the sdi pin into the receive buffer and out of the transmit buffer onto the sdo pin when cs is low. serial data output 6 sdo -serial port data output pin.sdo is forced into a high impedance state when cs is high. chip select 7 cs - low, activates the serial port interface. mode select 8 mode - high, enables the ?auto-boot? mode. the mode pin is pull-down by an internal resistor. energy output 22, 25, 26 e3 , e1 , e2 - active low pulses with an out put frequency proportional to energy. reset 23 reset - a schmitt trigger input pin. low activates reset, all internal registers (some of which drive output pins) are set to their default states. interrupt 24 int - low, indicates that an enabled event has occurred. serial data input 27 sdi - serial port data input pin. data will be input at a rate determined by sclk. analog inputs/outputs differential voltage inputs 9,10 13, 14 vin1+, vin1-, vin2+, vin2- - differential analog input pins for the voltage channel. differential current inputs 19,20, 15,16 iin+, iin-, iin2+, iin2- - differential analog input pins for the current channel. voltage reference output 11 vrefout - the on-chip voltage reference output. t he voltage reference has a nominal magni- tude of 2.5 v and is referenced to the agnd pin on the converter. voltage reference input 12 vrefin - the input to this pin establishes the voltage reference for the on-chip modulator. power supply connections positive digital supply 3 vd + - the positive digital supply. digital ground 4 dgnd - digital ground. positive analog supply 18 va+ - the positive analog supply. analog ground 17 agnd - analog ground. power fail monitor 21 pfmon - the power fail monitor pin monitors the analog supply. if pfmon?s voltage threshold is tripped, a low-supply detect (lsd) even t is set in the status register. vrefin 12 voltage reference input vrefout 11 voltage reference output vin1- 10 differential voltage input vin1+ 9 differential voltage input mode 8 mode select cs 7 chip select sdo 6 serial data ouput sclk 5 serial clock dgnd 4 digital ground vd+ 3 positive digital supply cpuclk 2 cpu clock output xout 1 crystal out agnd 17 analog ground va+ 18 positive analog supply iin1- 19 differential current input iin1+ 20 differential current input pfmon 21 power fail monitor e3 22 high-frequency energy output reset 23 reset int 24 interrupt e1 25 energy output 1 26 sdi 27 serial data input xin 28 crystal in e2 energy output 2 vin2- 14 differential voltage input vin2+ 13 differential voltage input iin2- 15 differential current input iin2+ 16 differential current input
cs5467 ds714a1 7 advance release 3. characteristics & specifications recommended operating conditions analog characteristics ? min / max characteristics and specifications are gua ranteed over all recommended operating conditions. ? typical characteristics and specifications are meas ured at nominal supply voltages and ta = 25 c. ? va+ = vd+ = 5 v 5%; agnd = dgnd = 0 v; vrefin = +2.5 v. all voltages with respect to 0 v. ? mclk = 4.096 mhz. notes: 1. applies when the hpf option is enabled. 2. applies when the line frequency is equal to the pr oduct of the output word rate (owr) and the value of epsilon ( ). parameter symbol min typ max unit positive digital power supply vd+ 3.135 5.0 5.25 v positive analog power supply va+ 4.75 5.0 5.25 v voltage reference vrefin - 2.5 - v specified temperature range t a -40 - +85 c parameter symbol min typ max unit accuracy active power all gain ranges (note 1) input range 0.1% - 100% p active -0.1- % average reactive power all gain ranges (note 1 and 2) input range 0.1% - 100% q avg -0.2- % power factor all gain ranges (note 1 and 2) input range 1.0% - 100% input range 0.1% - 1.0% pf - - 0.2 0.27 - - % % current rms all gain ranges (note 1) input range 1.0% - 100% input range 0.1% - 1.0% i rms - - 0.1 0.17 - - % % % voltage rms all gain ranges (note 1) input range 5% - 100% v rms -0.1- % analog inputs (all channels) common mode rejection (dc, 50, 60 hz) cmrr 80 - - db common mode + signal -0.25 - va+ v analog inputs (current channels) differential input range (gain = 10) [(iin+) - (iin-)] (gain = 50) iin - - 500 100 - - mv p-p mv p-p total harmonic distortion (gain = 50) thd 80 94 - db crosstalk with voltage channel at full scale (50, 60 hz) --115-db input capacitance ic - 27 - pf effective input impedance eii 30 - - k ? noise (referred to input) (gain = 10) (gain = 50) n i - - - - 22.5 4.5 v rms v rms offset drift (without the high pass filter) od - 4.0 - v/c gain error (note 3) ge - 0.4 %
cs5467 8 ds714a1 advance release analog characteristics (continued) notes: 3. applies before system calibration. 4. all outputs unloaded. all inputs cmos level. 5. measurement method for psrr: vrefin ti ed to vrefout, va+ = vd+ = 5 v, a 150 mv (zero-to-peak) (60 hz) sinewave is imposed onto th e +5 v dc supply voltage at va+ and vd+ pins. the ?+? and ?-? input pins of both input channels are shorted to agnd. the cs5464 is then commanded to continuous conversion acquisition mode, and digital ou tput data is collected for the channel under test. the (zero-to-peak) value of the digital sinusoidal out put signal is determined, and this value is converted into the (zero-to-peak) value of the sinusoidal volt age (measured in mv) that would need to be applied at the channel?s inputs, in order to cause the same di gital sinusoidal output. this voltage is then defined as veq. psrr is (in db) : 6. when voltage level on pfmon is sagging, and lsd bit = 0, the voltage at which lsd is set to 1. 7. if the lsd bit has been set to 1 (because pfmon voltage fell below pmlo), this is the voltage level on pfmon at which the lsd bit can be permanently reset back to 0. parameter symbol min typ max unit analog inputs (voltage channel) differential input range [(vin+) - (vin-)] vin - 500 - mv p-p total harmonic distortion thd 65 75 - db crosstalk with current channel at full scale (50, 60 hz) --70-db input capacitance all gain ranges ic - 2.0 - pf effective input impedance eii 2 - - m ? noise (referred to input) n v --140v rms offset drift (without the hig h pass filter) od - 16.0 - v/c gain error (note 3) ge - 3.0 % temperature channel temperature accuracy t - 5 - c power supplies power supply currents (active state) i a+ i d+ (va+ = vd+ = 5 v) i d+ (va+ = 5 v, vd+ = 3.3 v) psca pscd pscd - - - 1.3 2.9 1.7 - - - ma ma ma power consumption active state (va+ = vd+ = 5 v) (note 4) active state (va+ = 5 v, vd+ = 3.3 v) stand-by state sleep state pc - - - - 33 20 7 10 36 23 - - mw mw mw uw power supply rejection ratio (50, 60 hz) (note 5) voltage channel current channel (gain = 50x) current channel (gain = 10x) psrr 48 68 60 55 75 65 - - - db db db pfmon low-voltage trigger threshold (note 6) pmlo 2.3 2.45 - v pfmon high-voltage po wer-on trip point (note 7) pmhi - 2.55 2.7 v psrr 20 150 v eq --------- - log ? =
cs5467 ds714a1 9 advance release voltage reference notes: 8. the voltage at vrefout is measured across th e temperature range. from these measurements the following formula is used to calculate the vrefout temperature coefficient:. 9. specified at maximum recommended output of 1 a, source or sink. digital characteristics ? min / max characteristics and specifications are gua ranteed over all recommended operating conditions. ? typical characteristics and specifications are meas ured at nominal supply voltages and ta = 25 c. ? va+ = vd+ = 5v 5%; agnd = dgnd = 0 v. all voltages with respect to 0 v. ? mclk = 4.096 mhz. parameter symbol min typ max unit reference output output voltage vrefout +2.4 +2.5 +2.6 v temperature coefficient (note 8) tc vref - 25 60 ppm/c load regulation (note 9) ? v r -610mv reference input input voltage range vrefin +2.4 +2.5 +2.6 v input capacitance - 4 - pf input cvf current - 100 - na parameter symbol min typ max unit master clock characteristics master clock frequency internal gate oscillator (note 11) mclk 2.5 4.096 20 mhz master clock duty cycle 40 - 60 % cpuclk duty cycle (note 12 and 13) 40 - 60 % filter characteristics phase compensation range (voltage channel, 60 hz) -2.8 - +2.8 input sampling rate dclk = mclk/k - dclk/8 - hz digital filter output word rate (both channels) owr - dclk/1024 - hz high-pass filter corner frequency -3 db -0.5-hz full-scale dc calibration range (referred to input) (note 14) fscr 25 - 100 %f.s. channel-to-channel time-shift error (note 15) 1.0 s input/output characteristics high-level input voltage all pins except xin and sclk and reset xin sclk and reset v ih 0.6 vd+ (vd+) - 0.5 0.8 vd+ - - - - - - v v v low-level input voltage (vd = 5 v) all pins except xin and sclk and reset xin sclk and reset v il - - - - - - 0.8 1.5 0.2 vd+ v v v (vrefout max - vrefout min ) vrefout avg ( ( 1 t a max - t a min ( ( 1.0 x 10 ( ( 6 tc vref =
cs5467 10 ds714a1 advance release notes: 10. all measurements performed under static conditions. 11. if a crystal is used, xin frequency must remain be tween 2.5 mhz - 5.0 mhz. if an external oscillator is used, xin frequency range is 2.5 mhz - 20 mhz, but k must be set so that mclk is between 2.5 mhz - 5.0 mhz. 12. if external mclk is used, the duty cycle must be between 45% and 55% to maintain this specification. 13. the frequency of cpuclk is equal to mclk. 14. the minimum fscr is limited by the maximum allowe d gain register value. the maximum fscr is limited by the full-scale signal applied to the channel input. 15. configuration register bits pc[6:0] are set to ?0000000?. 16. the mode pin is pulled low by an internal resistor. low-level input voltage (vd = 3.3 v) all pins except xin and sclk and reset xin sclk and reset v il - - - - - - 0.48 0.3 0.2 vd+ v v v high-level output voltage i out = +5 ma v oh (vd+) - 1.0 - - v low-level output voltage i out =-5ma(vd=+5v) i out = -2.5 ma (vd = +3.3v) v ol - - - - 0.4 0.4 v v input leakage current (note 16) i in -110a 3-state leakage current i oz --10a digital output pin capacitance c out -5-pf parameter symbol min typ max unit
cs5467 ds714a1 11 advance release switching characteristics ? min / max characteristics and specifications are gua ranteed over all recommended operating conditions. ? typical characteristics and specifications are meas ured at nominal supply voltages and ta = 25 c. ? va+ = 5 v 5% vd+ = 3.3 v 5% or 5 v 5%; agnd = dgnd = 0 v. all voltages with respect to 0 v. ? logic levels: logic 0 = 0 v, logic 1 = vd+. notes: 17. specified using 10% and 90% points on waveform of interest. output loaded with 50 pf. 18. oscillator start-up time varies with crystal parameters. this specificat ion does not apply when using an external clock source. parameter symbol min typ max unit rise times (note 17) any digital output t rise - - - 50 1.0 - s ns fall times (note 17) any digital output t fall - - - 50 1.0 - s ns start-up oscillator st art-up time xtal = 4.096 mhz (note 18 ) t ost -60-ms serial port timing serial clock frequency sclk - - 2 mhz serial clock pulse width high pulse width low t 1 t 2 200 200 - - - - ns ns sdi timing cs falling to sclk rising t 3 50 - - ns data set-up time prior to sclk rising t 4 50 - - ns data hold time after sclk rising t 5 100 - - ns sdo timing cs falling to sdo driving t 6 -2050ns sclk falling to new data bit (hold time) t 7 -2050ns cs rising to sdo hi-z t 8 -2050ns auto-boot timing serial clock pulse width low pulse width high t 9 t 10 8 8 mclk mclk mode setup time to reset rising t 11 50 ns reset rising to cs falling t 12 48 mclk cs falling to sclk rising t 13 100 8 mclk sclk falling to cs rising t 14 16 mclk cs rising to driving mode low (to end auto-boot sequence) t 15 50 ns sdo guaranteed setup time to sclk rising t 16 100 ns
cs5467 12 ds714a1 advance release t 1 t 2 t 3 t 4 t 5 msb msb-1 lsb msb msb-1 lsb msb msb-1 lsb msb msb-1 lsb command time 8 sclks high byte mid byte low byte cs sclk sdi t 10 t 9 reset sdo sclk cs last 8 bits sdi mode stop bit d ata from e e p r o m t 16 t 4 t 5 t 14 t 15 t 7 t 13 t 12 t 11 (input) (input) (o u t p u t ) (o u t p u t ) (o u t p u t ) (input) t 1 t 2 msb msb-1 lsb command time 8 sclks sync0 or sync1 command sync0 or sync1 command msb msb-1 lsb msb msb-1 lsb msb msb-1 lsb high byte m id byte low byte cs sdo sclk sdi t 6 t 7 t 8 sync0 or sync1 command unknown sdi write timing (not to scale) sdo read timing (not to scale) figure 1. cs5464 read and write timing diagrams auto-boot sequence timing (not to scale)
cs5467 ds714a1 13 advance release switching characteristics (continued) notes: 19. pulse output timing is specified at mclk = 4.096 mhz, e2mode = 0, and e3mode[1:0] = 0. refer to 5.5 energy pulse output on page 18 for more information on pulse output pins. 20. timing is proportional to the frequency of mclk. absolute maximum ratings warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not gu aranteed at these extremes . notes: 21. va+ and agnd must satisfy [(va+) - (agnd)] + 6.0 v. 22. vd+ and agnd must satisfy [(vd+) - (agnd)] + 6.0 v. 23. applies to all pins including continuous over-v oltage conditions at the analog input pins. 24. transient current of up to 10 0 ma will not cause scr latch-up. 25. maximum dc input current for a power supply pin is 50 ma. 26. total power dissipation, including all input currents and output currents. parameter symbol min typ max unit e1 , e2 , and e3 timing (note 19 and 20) period t period 250 - - s pulse width t pw 244 - - s rising edge to falling edge t 3 6- - s e2 setup to e1 and/or e3 falling edge t 4 1.5 - - s e1 falling edge to e3 falling edge t 5 248 - - s parameter symbol min typ max unit dc power supplies (notes 21 and 22 ) positive digital positive analog vd+ va+ -0.3 -0.3 - - +6.0 +6.0 v v input current, any pin except supplies (notes 23, 24, 25) i in --10ma output current, any pin except vrefout i out --100ma power dissipation (note 26) p d --500mw analog input voltage all analog pins v ina - 0.3 - (va+) + 0.3 v digital input voltage all digital pins v ind -0.3 - (vd+) + 0.3 v ambient operating temperature t a -40 - 85 c storage temperature t stg -65 - 150 c t period e1 t 3 t 4 t 5 t 3 t 5 t 4 e2 e3 t pw t period t pw figure 2. timing diagram for e1 , e2 , and e3
cs5467 14 ds714a1 advance release 4. theory of operation the cs5467 is a four-channel analog-to-digital convert- er (adc) followed by a computation engine that per- forms power calculations and energy-to-pulse conversion. the data flow for the voltage and current channel measurement and the power calculation algo- rithms are depicted in figures 3 , 4 , and 5 . the cs5467 analog inputs are structured with two cur- rent channels and two voltage channels, and are opti- mized to simplify interfacing to various sensing elements. as shown in figures 3 and 4 , the current and voltage channels are fully independent. the voltage-sensing elements introduces a voltage waveform on the two voltage channel inputs vin and vin2 , which is subject to a gain of 10x. a second-order delta-sigma modulator samples the amplified signal for digitization. simultaneously, the current-sensing elements introduce a voltage waveform on the two current channel inputs iin and iin2 , which is subject to the two selectable gains of the programmable gain amplifier (pga). the amplified signals are sampled by a fourth-order delta-sigma modulator for digitization. the converters sample at a rate of mclk/8. the over-sampling pro- vides a wide dynamic range and simplified anti-alias fil- ter design. 4.1 digital filters the decimating digital filters on the four channels are sinc 3 filters followed by 3rd-order iir filters. the sin- gle-bit data is passed to the low-pass decimation filter and output at a fixed word rate. the output word is passed to an iir filter to compensate for the magnitude roll off of the low-pass filtering operation. an optional digital high-pass filter ( hpf in figures 3 and 4 ) removes any dc component from the selected signal path. by removing the dc component from the voltage and/or the current channel, any dc content will also be removed from the calculated active power as well. with both hpfs enabled the dc component will be removed voltage sinc 3 + x v gn current sinc 3 + x i gn delay reg i dcoff v dcoff pga + + control register digital filter digital filter hpf 2nd order ? modulator 4th order ? modulator x10 x x 7 delay reg hpf v q 0 1 2 2322 ... x x x q 2 mux x v p i mux vhpf ihpf 65 apf hpf apf iir 3 ... operational modes register iir sys gain sys gain pc[6] pc[5] pc[4] pc[3] pc[2] pc[1] pc[0] pc[7] register names indicated in shaded areas. iir figure 3. data measurement flow diagram 2nd order ? modulator control register + x v2 gn + x i2 gn i2 dcoff v2 dcoff pga + + hpf 4th order ? modulator hpf v2 q 0 1 2 2322 ... x x x q2 mux x v2 p2 i2 mux vhpf ihpf 87 apf hpf apf 3 current 2 ... operational modes register sinc 3 sinc 3 delay reg digital filter digital filter x x 7 delay reg iir iir sys gain sys gain iir pc[6] pc[5] pc[4] pc[3] pc[2] pc[1] pc[0] pc[7] register names indicated in shaded areas. x10 voltage 2 figure 4. data measurement flow diagram
cs5467 ds714a1 15 advance release from the calculated v rms and i rms , as well as the ap- parent power. when the optional hpf in either channel is disabled, an all-pass filter (apf ) in the complementary channel is im- plemented. the apf has an amplitude response that is flat within the channel bandwidth and is used for match- ing phase in systems where only one channel?s hpf is engaged. 4.2 voltage and current measurements the digital filter output word is subject to a dc-offset ad- justment and a gain calibration (see section 7. system calibration on page 39). the calibrated measurement is available by reading the instantaneous voltage and cur- rent registers. the root mean square ( rms in figure 5 ) calculations are performed on n instantaneous voltage and current samples, v n and i n , respectively (where n is the cycle count), using the formula: and likewise for v rms , using v n . i rms and v rms are ac- cessible by register reads, which are updated once ev- ery cycle count (referred to as a computational cycle). 4.3 power measurements the instantaneous voltage and current samples are multiplied to obtain the instantaneous power (see fig- ure 3 and 4 ). the product is then averaged over n con- versions to compute active power. the average active power measured on channels 1 and 2 is used to drive energy pulse output e1 . energy output e2 is config- urable and can provide an energy sign or a pulse output that is proportional to the average apparent power mea- sured on channels 1 and 2. energy output e3 provides a pulse output that is pro portional to the average reac- tive power or the average apparent power measured on channels 1 and 2. output e3 can also be set to indicate the pfmon comparator output or to indicate the sign of the voltage applied to the voltage channel. the apparent power (s, s2) is the combination of the active power and reactive power, without reference to an impedance phase angle, and is calculated by the cs5467 using the following formula: power factor (pf, pf2) is the active power (p active , p2 active ) divided by the apparent power (s, s2) the sign of the power factor is determined by the active power. i rms i n n0 = n1 ? n -------------------- - = i acoff (i2 acoff ) x v (v2) i rms (i2 rms ) v rms (v2 rms ) i (i2) energy-to-pulse x + + x + + + v acoff (v2 acoff ) + n n n n p active (p2 active ) n n pulseratee x s (s2) q avg (q2 avg ) - + x inverse x pf (pf2) q trig (q2 trig ) n n x e3 e2 e1 p off (p2 off ) q (q2) p (p2) register names (channel 2 register names) indicated in shaded areas. figure 5. power calculation flow sv rms i rms = pf p active s ------------------ =
cs5467 16 ds714a1 advance release the cs5467 calculates the reactive power (q trig , q2 trig ) utilizing trigonometric id entities, using the formu- la the average reactive power calculation (q avg , q2 avg ) is generated by averaging the voltage and multiplying that value by the current measurement with a 90 phase dif- ference between the two. the 90 phase shift is realized by applying an iir digital filter in the voltage channel to obtain quadrature voltage (see figure 3 and 4 ). this fil- ter will give exactly -90 ph ase shift across all frequen- cies, and utilizes epsilon ( ) to achieve unity gain at the line frequency. the instantaneous quadrature voltage (v q , v2 q ) and current (i, i2) samples are multiplied to obtain the in- stantaneous quadrature powe r (q, q2). the product is then averaged over n conver sions, utilizing the formula the peak current (i peak , i2 peak ) and peak voltage (v peak , v2 peak ) are the instantaneous current and voltage, re- spectively, with the greatest magnitude detected during the previous computation cycle. active, apparent, reac- tive, and fundamental power are updated every compu- tation cycle. 4.4 linearity performance the linearity of the v rms , i rms , active, reactive, and power-factor power measurements (before calibration) will be within 0.1% of read ing over the ranges speci- fied, with respect to the input voltage levels required to cause full-scale readings in the i rms and v rms regis- ters. refer to accuracy specifications on page 7. until the cs5467 is calibrated, the accuracy of the cs5467 (with respect to a reference line-voltage and line-current level on the power mains) is not guaranteed q trig s 2 p active 2 ? = q avg q n n1 = n n ------------------------ - =
cs5467 ds714a1 17 advance release 5. functional description 5.1 analog inputs the cs5467 is equipped with four fully differential input channels. the inputs vin , vin2 , iin , and iin2 are designated as the voltage, vo ltage 2, current, and cur- rent 2 channel inputs, respec tively. the full-scale differ- ential input voltage for the current and voltage channel is 250 mv p . 5.1.1 voltage channel input the output of the line voltage resistive divider or trans- former is connected to the vin+ (vin2+) and vin- (vin2-) input pins of the cs5467. the voltage channels are equipped with a 10x fixed-gain amplifier. the full-scale signal level that can be applied to the voltage channel is 250 mv. if the input signal is a sine wave, the maximum rms voltage at a gain 10x is: which is approximately 70.7% of maximum peak volt- age. the voltage channel is also equipped with a volt- age gain register , allowing for an additional programmable gain of up to 4x. 5.1.2 current channel inputs the output of the current-se nse resistor or transformer is connected to the iin+ (iin2+) and iin- (iin2-) input pins of the cs5467. to accommodate different cur- rent-sensing elements, the current channel incorpo- rates a programmable gain amplifier (pga) with two programmable input gains. configuration register bit igain (i2gain) defines the two gain selections and corre- sponding maximum input signal level. for example, if igain=0 (i2gain=0), current channel 1(2) pga gain is set to 10x. if the input signals are pure si- nusoids with zero phase shift, the maximum peak differ- ential signal on the current or voltage channel is 250 mv p . the input signal levels are approximately 70.7% of maximum peak voltage and produce a full-scale energy pulse registration equal to 50% of ab- solute maximum en ergy registration. this will be dis- cussed further in see section 5.5 energy pulse output on page 18. the current gain register also facilitates an additional programmable gain of up to 4x. if an additional gain is applied to the voltage and/or current channel, the maxi- mum input range should be adjusted accordingly. 5.2 iir filters the current and voltage channels are equipped with a 3rd-order iir filter, that is used to compensate for the magnitude roll off of the low-pass decimation filter. 5.3 high-pass filters by removing the offset from either channel, no error component will be generated at dc w hen computing the active power. by removing the offset from both chan- nels, no error component w ill be generated at dc when computing v rms , i rms , and apparent power. operation- al mode register bits vhpf, vhpf2, ihpf and ihpf2 activate the hpf in the voltage and current channel, re- spectively. when a high-pass f ilter is active in only one channel, an all-pass filter ( apf) is applied to the com- panion channel. the apf has an amplitude response that is flat within the chan nel bandwidth and is used for matching phase in systems where only one hpf is en- gaged. 5.4 performing measurements the cs5467 performs measurements of instantaneous voltage (v n ) and current (i n ), and calculates instanta- neous power (p n ) at an output word rate (owr) of where k is the value of the clock divider selected in the configuration register by bits k[3:0]. note that a value of k[3:0] = 0000 results in a clock divider setting of 16, rather than zero. the rms voltage (v rms , v2 rms ), rms current (i rms , i2 rms ), and active power (p active , p2 active ) are comput- ed using n instantaneous samples of v n , i n , and p n re- spectively, where n is the value in the cycle count register and is referred to as a ? computation cycle ?. the apparent power (s, s2) is the product of v rms and i rms . a computation cycle is derived from the master clock (mclk), with frequency: under default conditions and with k = 1, n = 4000, and mclk = 4.096 mhz ? the owr = 4000 and the computation cycle = 1 hz. igain, i2gain maximum input gain 0250mv10x 1 50 mv 50x table 1. current channel pga setting 250mv p 2 --------------------- 176.78mv rms ? owr mclk k ? () 1024 ----------------------------- = computation cycle owr n --------------- =
cs5467 18 ds714a1 advance release all measurements are available as a percentage of full scale. the format for signed registers is a two?s comple- ment, normalized value between -1 and +1. the format for unsigned registers is a normalized value between 0 and 1. a register value of represents the maximum possible value. at each instantaneous measurement, the crdy bit will be set in the status register , and the int pin will be- come active if the crdy bit is unmasked in the mask register . at the end of each computation cycle, the drdy bit will be set in the status register , and the int pin will become active if the drdy bit is unmasked in the mask register . when these bits are asserted, they must be cleared before they can be asserted again. if the cycle count register (n) is set to 1, all output cal- culations are instantaneou s, and drdy, like crdy, will indicate when instantaneous measurements are fin- ished. some calculations are inhibited when the cycle count is less than 2. epsilon ( ) is the ratio of the input line frequency (f i ) to the sample frequency (f s ) of the adc. where f s = mclk / (k x 1024). with mclk = 4.096 mhz and clock divider k = 1, f s = 4000 hz. for the two most-common line frequencies, 50 hz and 60 hz and respectively. epsilon is used to set the gain of the 90 phase shift (iir) filter for the average reactive power cal- culation. 5.5 energy pulse output the cs5467 provides three output pins for energy reg- istration. by default, e1 is used to register average ac- tive energy measured on channels 1 and 2, e3 is used to register average reactive energy measured on chan- nels 1 and 2, and e2 indicates the sign of both active and reactive energy. (see figure 2. timing diagram for e1, e2, and e3 on page 13.) the e1 pulse output is designed to indicate the average active energy measured on channels 1 and 2. the e2 pin can be used to register average apparent energy measured on channels 1 and 2 or to indicate the sign of energy. table 2 defines the pulse output mode, which is controlled by bit e2mode in the operational mode reg- ister. the e3 pin can be set to register average reactive ener- gy measured on channels 1 and 2 (default), pfmon, voltage channel sign, or average apparent energy mea- sured on channels 1 and 2. table 3 defines the pulse output format, which is controlled by bits e3mode[1:0] in the operational mode register. the pulse output frequencies of e1 , e2 , and e3 are di- rectly proportional to the power calculated from the input signals. the value contained in the pulseratee regis- ter is the ratio of the freque ncy of energy-output pulses to the number of samples, at full scale, which defines the average frequency for the output pulses. the pulse width, t pw in figure 2 , is an integer multiple of mclk cy- cles approximately equal to: if mclk = 4.096 mhz and k = 1 then t pw ? 0.25 ms. 5.5.1 active energy the e1 pin produces active-low pulses with an output frequency proportional to the average active power measured on channels 1 and 2. the e2 pin is the ener- gy direction indicator. posi tive energy is represented by e1 pin falling while the e2 is high. negative energy is represented by the e1 pin falling while the e2 is low. the e1 and e2 switching characteristics are specified in figure 2. timing diagram for e1, e2, and e3 on page 13. 2 23 1 ? () 2 23 ----------------------- - 0.99999988 = f i f s ? = 50 hz 4000 hz ? 0.0125 == 60 hz 4000 hz ? 0.015 == e2mode e2 output mode 0 sign of energy 1 apparent energy table 2. e2 pin configuration e3mode1 e3mode0 e3 output mode 0 0 reactive energy 01 pfmon 1 0 voltage channel sign 1 1 apparent energy table 3. e3 pin configuration t pw sec () 1 ( mclk/k ) / 1024 ------------------------------------ - ?
cs5467 ds714a1 19 advance release figure 6 illustrates the pulse outp ut format with positive active energy and negative reactive energy. the pulse output frequency of e1 is directly proportional to the active power calculated from the input signals. to calculate the output frequency of e1 , the following trans- fer function can be utilized: with mclk = 4.096 mhz, pf = 1, and default settings, the pulses will have an aver age frequency equal to the frequency specified by pulseratee when the input sig- nals applied to the voltage and current channels cause full-scale readings in the instantaneous voltage and cur- rent registers. the maximum pulse frequency from the e1 pin is (mclk/k)/2048. 5.5.2 apparent energy mode pin e2 outputs apparent energy pulses when the oper- ational mode register bit e2mode = 1. pin e3 outputs apparent energy pulses when the operational mode register bits e3mode[1:0] = 3 (11b). figure 7 illus- trates the pulse output format with apparent energy on e2 (e2mode = 1 and e3mode[1:0] = 0) the pulse output frequency of e2 (and/or e3 ) is directly proportional to the apparent power calculated from the input signals. since apparent power is without reference to an impedance phase angle, the following transfer function can be utilized to ca lculate the ou tput frequency on e2 (and/or e3 ). with mclk = 4.096 mhz and default settings, the puls- es will have an average freq uency equal to the frequen- cy specified by pulseratee when the input signals applied to the voltage and current channels cause full-scale readings in the in stantaneous voltage and cur- rent registers. the maximum pulse frequency from the e2 (and/or e3 ) pin is (mclk/k)/2048. the e2 (and/or e3 ) pin outputs apparent energy, but has no energy di- rection indicator. 5.5.3 reactive energy mode reactive energy pulses are output on pin e3 by setting bit e3mode[1:0] = 0 (default) in the operational mode register . positive reactive energy is registered by e3 falling when e2 is high. negative reactive energy is reg- istered by e3 falling when e2 is low. figure 6 on page 19 illustrates the pulse ou tput format with negative reactive energy output on pin e3 and the sign of the en- ergy on e2 . the e3 and e2 pulse output switching char- acteristics are specified in figure 2 on page 13. the pulse output frequency of e3 is directly proportional to the reactive power calculated from the input signals. to calculate the output frequency on e3 , the following transfer function can be utilized: with mclk = 4.096 mhz, pf = 0 and default settings, the pulses will have an aver age frequency equal to the frequency specified by pulseratee when the input sig- nals applied to the voltage and current channels cause full-scale readings in the in stantaneous voltage and cur- e3 e2 e1 figure 6. active and reactive energy pulse outputs where freq p = average frequency of active energy e1 pulses [hz] vin(2) = rms voltage across vin(2)+ and vin(2)- [v] v(2)gain = voltage channel gain iin(2) = rms voltage across iin(2)+ and iin(2)- [v] i(2)gain = current channel gain pf(2) = power factor pulserate = pulseratee x (mclk/k)/2048 [hz] vrefin = voltage at vrefin pin [v] freq p p active p2 active + () 2 ? [] pulserate = p2 () active vin 2 () v2 () gain iin 2 () i2 () gain pf 2 () vrefin 2 ------------------------------------------------------------------------------------------------------------------------------- ---- = e3 e2 e1 figure 7. apparent energy pulse outputs where freq s = average frequency of apparent energy e2 and/or e3 pulses [hz] vin(2) = rms voltage across vin(2)+ and vin(2)- [v] v(2)gain = voltage channel gain iin(2) = rms voltage across iin(2)+ and iin(2)- [v] i(2)gain = current channel gain pulserate = pulseratee x (mclk/k)/2048 [hz] vrefin = voltage at vrefin pin [v] freq s ss2 + () 2 ? [] pulserate = s2 () vin 2 () v2 () gain iin 2 () i2 () gain vrefin 2 ---------------------------------------------------------------------------------------------------------- - = where freq q = average frequency of reactive energy e3 pulses [hz] vin(2) = rms voltage across vin(2)+ and vin(2)- [v] v(2)gain = voltage channel gain iin(2) = rms voltage across iin(2)+ and iin(2)- [v] i(2)gain = current channel gain pq = pulserate = pulseratee x (mclk/k)/2048 [hz] vrefin = voltage at vrefin pin [v] freq q q avg q2 avg + () 2 ? [] pulserate = q2 () avg vin 2 () v2 () gain iin 2 () i2 () gain pq 2 () vrefin 2 ------------------------------------------------------------------------------------------------------------------------------- ----- = 1pf 2 ?
cs5467 20 ds714a1 advance release rent registers. the maximum pulse frequency from the e1 pin is (mclk/k)/2048. 5.5.4 voltage channel sign mode setting bits e3mode[1:0] = 2 (10b) in the operational mode register outputs the sign of the voltage channel on pin e3 . figure 8 illustrates the output format with volt- age channel sign on e3 output pin e3 is high when the line voltage is positive and pin e3 is low when the line voltage is negative. 5.5.5 pfmon output mode setting bit e3mode[1 :0] = 1 (01b) in the operational mode register outputs the state of the pfmon compar- ator on pin e3 . figure 9 illustrates the out put format with pfmon on e3 when pfmon is greater than the threshold, pin e3 is high and when pfmon is less than the threshold pin e3 is low. 5.6 sag and faul t detect feature status bit vsag (v2sag) and ifault (i2fault) in the status register, indicates a sag occurred in the power line voltage (voltage 2) and current (current 2), respec- tively. for a sag condition to be identified, the absolute value of the instantaneous voltage or current must be less than the sag level for more than half of the sag du- ration (see figure 10 ). to activate voltage sag det ection, a voltage sag level must be specified in the voltage sag level register (vsag level , v2sag level ), and a voltage sag duration must be specified in the voltage sag duration register (vsag duration, v2sag duration ). to activate current fault detection, a current sag leve l must be specified in the current fault level register (isag level, i2sag level ), and a current sag duration must be specified in the current fault duration register (isag duration, i2sag duration ). the voltage and current sag levels are specified as the average of the absolute instantaneous voltage and cur- rent, respectively. voltage and current sag duration is specified in terms of adc cycles. 5.7 on-chip temperature sensor the on-chip temperature sensor is designed to assist in characterizing the measurement element over a desired temperature range. once a temperature characteriza- tion is performed, the temperature sensor can be uti- lized to assist in compensating for temperature drift. temperature measurements are performed when a one is written to the temperature measurement (t meas ) reg- ister and stored in the temperature register . the tem- perature register (t) default is celsius scale (c). the temperature gain register (t gain ) and temperature offset register (t off ) are constant values allowing for temperature scale conversions. the temperature update rate is a function of the number of adc samples. with mclk = 4.096 mhz and k = 1 the update rate is: the cycle count register (n) must be set to a value greater than one. status bit tup in the status register, indicates when the temperature register is updated. the temperature offset register sets the zero-degree measurement. to improve temperature measurement accuracy, the zero-degree offset may need to be adjust- ed after the cs5467 is initialized. temperature-offset calibration is achieved by adjusting the temperature offset register (t off ) by the differential temperature ( ? t) measured from a calibrated digital thermometer and the cs5467 temperature sensor. a one-degree ad- justment to the temperature register (t) is achieved by e3 e2 e1 figure 8. voltage channel sign pulse outputs e3 e2 e1 above pfmon threshold below pfmon threshold figure 9. pfmon output to pin e3 level duration figure 10. sag and fault detect 2240 samples mclk k ? () 1024 ? --------------------------------------- - 0.56 sec =
cs5467 ds714a1 21 advance release adding 2.737649x10 -4 to the temperature offset regis- ter (t off ). therefore, if t off = -0.094488 and ? t = -2.0 (c), then or 0xf3d5bb (2?s compliment notation) is stored in the temperature offset register (t off ). to convert the temperature register (t) from a celsius scale (c) to a fahrenheit scale (f) utilize the formula applying the above relationship to the cs5461a tem- perature measurement algorithm if t off = -0.09504 and t gain = 26.443 for a celsius scale, the modified values are t off = -0.09017 (0xf47550) and t gain = 47.6 (0x5f3333) for a fahrenheit scale. 5.8 voltage reference the cs5467 is specified for operation with a +2.5 v ref- erence between the vrefin and agnd pins. to utilize the on-chip 2.5 v reference, connect the vrefout pin to the vrefin pin of the device. the vrefin can be used to connect external filtering and/or references. 5.9 system initialization upon powering up, the digital circuitry is held in reset until the analog voltage reaches 4.0 v. at that time, an eight-xin-clock-period delay is enabled to allow the os- cillator to stabilize. the cs 5467 will then initialize. a hardware reset is initiated when the reset pin is as- serted with a minimum pulse width of 50 ns. the re- set signal is asynchronous, with a schmitt-trigger input. once the reset pin is de-asserted, an eight-xin-clock-perio d delay is enabled . a software reset is initiate d by writing the command 0x80. after a hardware or software reset, the internal registers (some of which drive output pins) will be reset to their default values. status bit drdy in the status register, indicates the cs5467 is in its active state and ready to receive commands. 5.10 power-down states the cs5467 has two power-down states, stand-by and sleep . in the stand-by state all circuitry except the volt- age referenc e and crystal oscillator is turned off. to re- turn the device to the active state, a power-up command is sent to the device. in sleep state, all circuitry except the instruction decod- er is turned off. when the power-up command is sent to the device, a system initia lization is performed (see section 5.9 system initialization on page 21). 5.11 oscillator characteristics xin and xout are the input and output of an inverting amplifier configured as an on-chip oscillator, as shown in figure 11 . the oscillator circuit is designed to work with a quartz crystal. to reduce circuit cost, two load ca- pacitors c1 and c2 are in tegrated in the device, from xin to dgnd, and xout to dgnd. pcb trace lengths should be minimized to re duce stray capacitance. to drive the device from an external clock source, xout should be left unconnected while xin is driven by the external circuitry. there is an amplifier between xin and the digital section which provides cmos level signals. this amplifier works with sinu soidal inputs so there are no problems with slow edge times. the cs5467 can be driven by an external oscillator ranging from 2.5 to 20 mhz, but the k divider value must be set such that the internal mclk will run somewhere between 2.5 mhz and 5 mhz. the k divider value is set with the k[3:0] bits in the configuration register . as an example, if xin = mclk = 15 mhz, and k is set to 5, dclk will equal 3 mhz, which is a valid value for dclk. 5.12 event handler the int pin is used to indicate that an internal error or event has taken place in the cs5467. writing a logic 1 t off t off ? t 2.737649 10 4 ? ? () + = t off 0.094488 ? 2.0 ? 2.737649 10 4 ? ? () + () 0.09504 ? == f o 9 5 -- -c o 17.7778 + () = tf o ?? 9 5 -- - t gain ?? ?? tc o ?? t off 17.7778 2.737649 10 4 ? ? () + ?? ?? + = oscillator circuit dgnd xin xout c1 c1 = 22 pf c2 c2 = figure 11. oscillator connection
cs5467 22 ds714a1 advance release to any bit in the mask register allows the corresponding bit in the status register to activate the int pin. the in- terrupt condition is cleared by writing a logic 1 to the bit that has been set in the status register . the behavior of the int pin is controlled by the imode and iinv bits of the configuration register . if the interrupt ou tput signal format is set for either falling or rising edge, the duration of the int pulse will be at least one dclk cycle (dclk = mclk/k). 5.12.1 typical interrupt handler the steps below show how interrupts can be handled. initialization : 1) all status bits are cl eared by writing 0xffffff to the status register. 2) the condition bits whic h will be used to generate interrupts are set to logic 1 in the mask register. 3) enable interrupts. interrupt handler routine : 4) read the status register. 5) disable all interrupts. 6) branch to the proper interrupt service routine. 7) clear the status register by writing back the read value in step 4. 8) re-enable interrupt 9) return from interrupt service routine. this handshaking procedure ensures that any new in- terrupts activated between steps 4 and 7 are not lost (cleared) by step 7. 5.13 serial port overview the cs5467 incorporates a serial port transmit and re- ceive buffer with a command decoder that interprets one-byte (8-bit) commands as they are received. there are four types of commands: instructions, synchroniz- ing, register writes, and register reads (see section 5.15 commands on page 24). instructions are one byte in length and will interrupt any instruction currently executing. instructions do not affect register reads currently being transmitted. synchronizing commands are one byte in length and only affect the serial in terface. synchronizing com- mands do not affect operations currently in progress. register writes must be followed by three bytes of data. register reads can return up to four bytes of data. commands and data are transf erred most-significant bit (msb) first. figure 1 on page 12, defines the serial port timing and required sequence necessary for writing to and reading from the serial port receive and transmit buffer, respectively. while reading data from the serial port, commands and data can be written simultaneous- ly. starting a new register read command while data is being read will term inate the current read in progress. this is acceptable if the remainder of the current read data is not needed. during data reads, the serial port re- quires input data. if a new command and data is not sent, sync0 or sync1 must be sent. 5.13.1 serial port interface the serial port interface is a ?4-wire? synchronous serial communications interface. the interface is enabled to start excepting sclks when cs (chip select) is assert- ed (logic 0). sclk (serial bit-clock) is a schmitt-trigger input that is used to strobe the data on sdi (serial data in) into the receive buffer and out of the transmit buffer onto sdo (serial data out). imode iinv int pin 0 0 active-low level 0 1 active-high level 10 low pulse 11 high pulse table 4. interrupt configuration
cs5467 ds714a1 23 advance release if the serial port interface becomes unsynchronized with respect to the sclk input, any attempt to clock valid commands into the serial interface may result in unex- pected operation. therefor, the serial port interface must be re-initialized by one of the following actions: -drive the cs pin high, then low. - hardware reset (drive reset pin low for at least 10 s). - issue the serial port initialization sequence , which is 3 (or more) sync1 command bytes (0xff) followed by one sync0 command byte (0xfe). if a re-synchronization is necess ary, it is best to re-ini- tialize the part either by hardware or software reset (command 0x80), as the state of the part may be un- known. 5.14 register paging read/write commands access one of the 32 registers within a specified page. by default, page = 0. to access registers in another page, the page register (address 0x1f) must be written with the desired page number. example: reading register 6 in page 3. 1. write 3 to page register with command and data: 0x7e 0x00 0x00 0x03 2. read register 6 with command: 0x0c 0xff 0xff 0xff 0xfff 0x000 0x3ff hardware registers* 32 pages software register* 32 pages rom 2048 words 0x400 0x7ff 0x800 pages 0x40 - 0x7f pages 0x20 - 0x3f pages 0 - 0x1f * accessed using register read/write commands. figure 12. cs5467 memory map
cs5467 24 ds714a1 advance release 5.15 commands all commands are 8 bits in length. any command byte value that is not listed in this section is invalid. commands that write to registers must be followed by 3 bytes of da ta. commands that read data c an be chained with other com- mands (e.g., while reading data, a new command can be sent which can execute during the original read). all com- mands except register reads, register writes, and sy nc0 & sync1 will abort any currently executing commands. 5.15.1 start conversions initiates acquiring measurements and calculating results. the device has two modes of acquisition. c3 modes of acquisition/measurement 0 = perform a single computation cycle 1 = perform continuou s computation cycles 5.15.2 sync0 and sync1 the serial port is resynchronized to byte boundaries by sending three or more consecutive sync1 commands fol- lowed by a sync0 command. the sync0 or sync1 commands can also be used as a nop command. sync designates calibration 0 = this command is the end of the serial port re-initialization sequence. 1 = this command is part of the seri al port re-initialization sequence. 5.15.3 power-down, power-up, halt and software reset to conserve power the cs5467 has two po wer-down states. in stand- by state all circuitry, except the analog/digital clock generators, is turned off. in the sleep state all circ uitry, except the digital clock generator and the command decoder, is turned off. bringing the cs5467 out of sleep state requires more time than bringing it out of stand-by state, because of the extra time needed to re-start and re-stabiliz e the analog clock signal. if the device is pow- ered-down, power-up/halt will in itiate a power on rese t. if the part is already power ed-on, all comput ations will be halted. s[1:0] power-down state 00 = software reset 01 = halt and enter sleep power saving stat e. this state requires a slow power-on time 10 = power-up and halt 11 = halt and enter stand-by power saving state. this state allows quick power-on time b7 b6 b5 b4 b3 b2 b1 b0 1110c3000 b7 b6 b5 b4 b3 b2 b1 b0 1111111sync b7 b6 b5 b4 b3 b2 b1 b0 10s1s00000
cs5467 ds714a1 25 advance release 5.15.4 register read/write the read/write informs the command decoder that a register access is required. during a read operation, the ad- dressed register is loaded into the device?s output buffer and clocked out by sclk. during a write operation, the data is clocked into the input buffer and transferred to the addressed register upon completion of the 24 th sclk. w/r write/read control 0 = read register 1 = write register ra[4:0] register address bits (bits 5 through 1) of the read/write command. page 0 address ra[4:0] name description 0 00000 config configuration 1 00001 i instantaneous current 2 00010 v instantaneous voltage 3 00011 p instantaneous power 4 00100 p active average active (real) power 5 00101 i rms rms current 6 00110 v rms rms voltage 7 00111 i2 instantaneous current 2 8 01000 v2 instantaneous voltage 2 9 01001 p2 instantaneous power 2 10 01010 p2 active average active (real) power 2 11 01011 i2 rms rms current 2 12 01100 v2 rms rms voltage 2 13 01101 q avg average reactive power 14 01110 q instantaneous reactive power 15 01111 status status (write of ?1? to status bit will clear the bit) 16 10000 q2 avg average reactive power 2 17 10001 q2 instantaneous reactive power 2 18 10010 i peak peak current 19 10011 v peak peak voltage 20 10100 s apparent power 21 10101 pf power factor 22 10110 i2 peak peak current 2 23 10111 v2 peak peak voltage 2 24 11000 s2 apparent power 2 25 11001 pf2 power factor 2 26 11010 mask mask 27 11011 t temperature 28 11100 ctrl control 29 11101 p pulse active energy pulse output accumulator 30 11110 s pulse apparent energy pulse output accumulator 31 11111 q pulse / page reactive energy pulse output accumulator (read only) and page (write only) note: for proper operation, do not attempt to write to unspecified registers. b7 b6 b5 b4 b3 b2 b1 b0 0w/r ra4 ra3 ra2 ra1 ra0 0
cs5467 26 ds714a1 advance release page1 address ra[4:0] name description 0 00000 i dcoff current dc offset 1 00001 i gn current gain calibration 2 00010 v dcoff voltage dc offset 3 00011 v gn voltage gain calibration 4 00100 p off power offset 5 00101 i acoff current ac (rms) offset 6 00110 v acoff voltage ac (rms) offset 7 00111 i2 dcoff current dc offset 2 8 01000 i2 gn current gain calibration 2 9 01001 v2 dcoff voltage dc offset 2 10 01010 v2 gn voltage gain calibration 2 11 01011 p2 off power offset 2 12 01100 i2 acoff current ac (rms) offset 2 13 01101 v2 acoff voltage ac (rms) offset 2 15 01111 pulseratee sets the energy-to-frequency output pulse rate 16 10000 mode operational modes 17 10001 epsilon epsilon 19 10011 cycle count number of conversions in one computation cycle (n) 20 10100 q trig reactive power calculated from power triangle 21 10101 q2 trig reactive power calculated from power triangle 2 22 10110 t gain temperature sensor gain 23 10111 t off temperature sensor offset 26 11010 t meas temperature measurement 28 11100 sys gain system gain page2 address ra[4:0] name description 0 00000 vsag duration vsag duration 1 00001 vsag level vsag level 4 00100 isag duration isag duration 5 00101 isag level isag level 8 01000 v2sag duration vsag duration 2 9 01001 v2sag level vsag level 2 12 01100 i2sag duration isag duration 2 13 01101 i2sag level isag level 2 note: for proper operation, do not attempt to write to unspecified registers.
cs5467 ds714a1 27 advance release 5.15.5 calibration the cs5467 can perform system calibrations. proper input signals must be applied to the current and voltage chan- nel before performing a designated calibration. cal[5:4]* designates calibration to be performed 00 = channel dc offset 01 = channel dc gain 10 = channel ac offset 11 = channel ac gain cal[3:0]* designates channel to calibrate 0001 = current channel 0010 = voltage channel 0100 = current channel 2 1000 = voltage channel 2 *by utilizing different combinations fo r cal[3:0], multiple ch annels can be calibrated simultaneously, e.g. cal[5:0] = 001111 commands the cs5467 to perform a dc offset calibration on all four channels. values for cal[5:0] not specified should not be used. b7 b6 b5 b4 b3 b2 b1 b0 1 0 cal5 cal4 cal3 cal2 cal1 cal0
cs5467 28 ds714a1 advance release 6. register description 1. ?default? = bit status after power-on or reset 2. any bit not labeled is reserved. a zero should always be used when writing to one of these bits. 6.1 page 0 registers 6.1.1 configuration (config) register address: 0 default = 0x000001 pc[7:0] phase compensation. sets a delay in the volt age channel relative to the current channel 1. de- fault setting is 00000000 = 0.0215 degree phase delay at 60 hz (when mclk = 4.096 mhz). ewa allows the e1 and e2 pins to be configured as open-collector output pins. 0 = normal outputs (default) 1 = only the pull-down device of the e1 and e2 pins are active imode, iinv soft interrupt configuration bits. select the desired pin behavior for indication of an interrupt. 00 = active-low level (default) 01 = active-high level 10 = low pulse 11 = high pulse icpu inverts the cpuclk clock. in order to reduce the level of noise present when analog signals are sampled, the logic driven by cpuclk should not be active during the sample edge. 0 = normal operation (default) 1 = minimize noise when cpuclk is driving rising edge logic k[3:0] clock divider. a 4-bit binary number used to di vide the value of mclk to generate the internal clock dclk. the internal clock frequency is dclk = mclk/k. the value of k can range be- tween 1 and 16. note that a va lue of ?0000? will set k to 16 (not zero). k = 1 at reset. 23 22 21 20 19 18 17 16 pc[7] pc[6] pc[5] pc[4] pc[3] pc[2] pc[1] pc[0] 15 14 13 12 11 10 9 8 ewa - - imode iinv - - - 76543210 - - - icpu k[3] k[2] k[1] k[0]
cs5467 ds714a1 29 advance release 6.1.2 instantaneous current (i, i2), voltage (v, v2), and power (p, p2) registers address: 1 (i), 2 (v), 3 (p), 7 (i2), 8 (v2), 9 (p2) i (i2) and v (v2)contain the instantaneous measured valu es for current and voltage, respectively. the instanta- neous voltage (voltage 2) and current (current 2) samp les are multiplied to obtain instantaneous power, p (p2). the value is represented in two's complement notation and in the range of -1.0 i, v, p < 1.0 (-1.0 i2, v2, p 2 < 1.0), with the binary point to the right of the msb. 6.1.3 active (real) power (p active , p2 active ) registers address: 4 (p active ), 10 (p2 active ) the instantaneous power is averaged over each computat ion cycle (n conversions) to compute active power, p active (p2 active ). the value will be with in in the range of -1.0 p active < 1.0 (-1.0 p2 active < 1.0). the value is rep- resented in two's complement notation, with the binary point to the right of the msb. 6.1.4 rms current (i rms , i2 rms ) & voltage (v rms , v2 rms ) registers address: 5 (i rms ), 6 (v rms ), 11 (i2 rms ), 12 (v2 rms ) i rms (i2 rms ) and v rms (v2 rms ) contain the root mean square (rms) valu es of i (i2) and v (v2), calculated each computation cycle. the value is represented in unsigned binary notation and in the range of 0.0 i rms ,v rms < 1.0 (0.0 i2 rms ,v2 rms < 1.0), with the binary point to the left of the msb. 6.1.5 instantaneous reactive power (q, q2) registers address: 14 (q), 17 (q2) the instantaneous reactive power (q, q2) is the product of the voltage (voltage 2) signal, shifted 90 degrees, and the current (current 2) signal. the value is repres ented in two's complement notation and in the range of -1.0 < q < 1.0 (1.0 < q2 < 1.0), with the binary point to the right of the msb. 6.1.6 average reactive power (q avg , q2 avg ) registers address: 13 (q avg ), 16 (q2 avg ) the average reactive power (q avg , q2 avg ) is q (q2) averaged over n samples. the value is represented in two's complement notation and in the range of -1.0 < q avg < 1.0 (-1.0 < q2 avg < 1.0), with the binary point to the right of the msb. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 ..... 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 2 -24 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23
cs5467 30 ds714a1 advance release 6.1.7 status (status) and mask (mask) register address: 15 ( status ) ; 26 (mask) default = 0x800001 (status register), 0x000000 (mask register) the status register indicates status within the chip. in normal operation, writing a '1 ' to a bit will cause the bit to reset. writing a '0 ' to a bit will not cha nge it?s current state. the mask register is used to control the activation of the int pin. placing a logic '1' in a mask bit will allow the corresponding bit in the status register to activate the int pin when the status bit is asserted. drdy data ready. during conversions, this bit will indicate the end of computation cycles. for cal- ibrations, this bit indicates the end of a calibration sequence. ior (i2or) current out of range. set when the m agnitude of the measured current value causes the i (i2) register to overflow. vor (v2or) voltage out of range. set when the magni tude of the measured voltage value causes the v (v2) register to overflow. crdy conversion ready. indicates a new conversion is r eady. this will occur at the output word rate. iror (i2ror) rms current out of range. set when the calculated rms current value causes the i rms (i2 rms ) register to overflow. vror (v2ror) rms voltage out of range. set when the calculated rms voltage value causes the v rms (v2 rms ) register to overflow. eor (e2or) energy out of range. set when p active (p2 active ) overflows. ifault (i2fault) indicates a current fault occurred in the power line current. if the absolute value of the in- stantaneous current is less than isag level (i2sag level ) for more than half of the isag duration (i2sag duration ), the ifault (i2fau lt) bit will be set. vsag (v2sag) indicates a voltage sag occurred in the power line voltage. if the absol ute value of the in- stantaneous voltage is less than vsag level (v2sag level ) for more than half of the vsag duration (v2sag duration ), the vsag (v2sag) bit will be set. tup temperature updated. indicates a temperature conversion is ready. vod (v2od) modulator oscilla tion detected on the vo ltage (voltage 2) channel . set when the modulator oscillates due to an input above full scale. the level at which the modulator oscillates is sig- nificantly higher than the voltage (voltage 2) channel?s differential input voltage range. iod (i2od) modulator oscillation de tected on the current (current 2) channel. set when the modulator oscillates due to an input above full scale. the level at which the modulator oscillates is sig- nificantly higher than the current (current 2) channel?s differential input voltage range. note: the iod (i2od) and vod (v2od) bits may be ?falsely? triggered by very brief voltage 23 22 21 20 19 18 17 16 drdy i2or v2or crdy i2ror v2ror ior vor 15 14 13 12 11 10 9 8 e2or iror vror eor ifault vsag i2fault v2sag 76543210 tup v2od i2od vod iod lsd fup ic
cs5467 ds714a1 31 advance release spikes from the power line. this event should not be confused with a dc overload situation at the inputs, when the iod (i 2od) and vod (v2od) bits will re-assert themselves even after being cleared, multiple times. lsd low supply detect. set when the voltage at th e pfmon pin falls below the low-voltage thresh- old (pmlo), with respect to agnd pin. for a given part, pmlo can be as low as 2.3 v. lsd bit cannot be permanently reset until the voltage at pfmon pin rises back above the high-voltage threshold (pmhi), which is typically 100 mv abov e the device?s low-volt age threshold. pmhi will never be greater than 2.7 v. fup epsilon updated. indicates an update to the ep silon value has been placed in the register. ic invalid command. normally logic 1. set to logic 0 if the host inte rface is strobed with an 8-bit word that is not recognized as one of the valid commands (see see section 5.15 commands on page 24). 6.1.8 peak current (i peak , i2 peak ) and peak voltage (v peak , v2 peak ) register address: 18 (i peak ), 19 (v peak ), 22 (i2 peak ), 23 (v2 peak ) the peak current (i peak , i2 peak ) and peak voltage (v peak , v2 peak ) registers contain the instantaneous current and voltage with the greatest magnit ude detected during the last comput ation cycle. the valu e is represented in two's complement notation and in the range of -1.0 i peak ,v peak < 1.0 (-1.0 i2 peak ,v2 peak < 1.0), with the binary point to the right of the msb. 6.1.9 apparent power (s, s2) register address: 20 (s), 24 (s2) apparent power s (s2) is the product of the v rms and i rms (v2 rms and i2 rms ), the value is represented in unsigned notation and in the range of 0 s < 1.0 (0 s2 < 1.0), with the binary point to the right of the msb. 6.1.10 power factor (pf, pf2) register address: 21 (pf), 25 (pf2) power factor is calculated by dividing the active (real) power by apparent power. the value is represented in two's complement notation and in the range of -1.0 pf < 1.0 (-1.0 pf2 < 1.0), with the binary point to the right of the msb. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23
cs5467 32 ds714a1 advance release 6.1.11 temperature (t) register address: 27 t contains measurements from the on-chip temperature sensor. measurements are performed during continu- ous conversions, with the default the celsius scale ( o c). the value is represented in two's complement notation and in the range of -128.0 t < 128.0, with the binary point to the right of the eighth msb. 6.1.12 control (crtl) register register address: 28 default = 0x000000 pc2[7:0] phase compensation. sets a delay in the volt age channel relative to current channel 2. default setting is 00000000 = 0.0215 degree phase de lay at 60 hz (when mclk = 4.096 mhz). igain (i2gain) sets the gain of the current (current 2) pga. 0 = gain is 10 (default) 1 = gain is 50 stop terminates the auto-boot sequence. 0 = normal (default) 1 = stop sequence intod converts int output pin to an open drain output. 0 = normal (default) 1 = open drain nocpu saves power by disabling the cpuclk pin. 0 = normal (default) 1 = disables cpuclk noosc saves power by disab ling the crystal oscillator. 0 = normal (default) 1 = disabling oscillator circuit msb lsb -(2 7 )2 6 2 5 2 4 2 3 2 2 2 1 2 0 ..... 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 2 -16 23 22 21 20 19 18 17 16 pc2[7] pc2[6] pc2[5] pc2[4] pc2[3] pc2[2] pc2[1] pc2[0] 15 14 13 12 11 10 9 8 ---i2gain---stop 76543210 - - igain intod - nocpu noosc -
cs5467 ds714a1 33 advance release 6.1.13 active energy pulse output accumulator (p pulse ) register address: 29 the active energy puls e output accumulator (p pulse ) contains the average active energy measured on chan- nels 1 & 2 and is used to drive the pulse output. the va lue is represented in two's complement notation and in the range of -1.0 p pulse < 1.0, with the binary point to the right of the msb. 6.1.14 apparent energy pulse output accumulator (s pulse ) register address: 30 the apparent energy pulse output accumulator (s pulse ) contains the average apparent power measured on channels 1 & 2 and is used to drive the pulse output. th is result is updated after each computation cycle. the value is represented in two's complement notation and in the range of -1.0 s pulse < 1.0, with the binary point to the right of the msb. 6.1.15 reactive energy pulse output accumulator (q pulse ) register address: 31 (read only) the reactive energy pulse output accumulator (q pulse ) contains the average reactive power measured chan- nels 1 & 2 and is used to drive the pulse output. the va lue is represented in two's complement notation and in the range of -1.0 q pulse < 1.0, with the binary point to the right of the msb. 6.1.16 page register address: 31 (write only) default = 0x00 determines which register pag e the serial port will access. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 2 6 2 5 2 4 2 3 2 2 2 1 2 0
cs5467 34 ds714a1 advance release 6.2 page 1 registers 6.2.1 current dc offset (i dcoff , i2 dcoff ) and voltage dc offset (v dcoff , v2 dcoff ) registers address: 0 (i dcoff ), 2 (v dcoff ), 7 (i2 dcoff ), 9 (v2 dcoff ) default = 0x000000 the dc offset registers (i dcoff ,v dcoff , i2 dcoff ,v2 dcoff ) are initialized to 0.0 on reset. when dc offset calibration is performed, the register is updated with the dc offset measured over a computati on cycle. drdy will be set at the end of the calibration. this register may be read and st ored for future system offset compensation. the value is represented in two's complement notation and in the range of -1.0 i dcoff ,v dcoff < 1.0 (-1.0 i2 dcoff ,v2 dcoff < 1.0), with the binary point to the right of the msb. see section 7.1.2.1 dc offset calibra- tion sequence on page 39 for more information. 6.2.2 current gain (i gn , i2 gn ) and voltage gain (v gn , v2 gn ) registers address: 1 (i gn ), 3 (v gn ), 8 (i2 gn ), 10 (v2 gn ) default = 0x400000 = 1.000 the gain registers (i gn ,v gn , i2 gn ,v2 gn ) are initialized to 1.0 on reset. when either a ac or dc gain calibration is performed, the register is updated with the gain measured over a com putation cycle. drdy will be set at the end of the calibration. this register may be read and st ored for future system gain compensation. the value is in the range 0.0 i gn ,v gn < 3.9999 (0.0 i2 gn ,v2 gn < 3.9999), with the binary poin t to the right of the second msb. 6.2.3 power offset (p off , p2 off ) registers address: 4 (p off ), 11 (p2 off ) default = 0x000000 power offset (p off , p2 off ) is added to the instantaneous power being accumulated in the p active (p2 active ) regis- ter, and can be used to offset contributions to the energy result that are caused by undesirable sources of energy that are inherent in the system. the value is represen ted in two's complement notation and in the range of -1.0 p off < 1.0 (-1.0 p2 off < 1.0), with the binary point to the right of the msb. 6.2.4 current ac offset (i acoff , i2 acoff ) and voltage ac offset (v acoff , v2 acoff ) registers address: 5 (i acoff ), 6 (v acoff ), 12 (i2 acoff ), 13 (v2 acoff ) default = 0x000000 the ac offset registers (v acoff , i acoff, v2 acoff , i2 acoff ) are initialized to zero on reset, allowing for uncalibrated normal operation. ac offset calibration updat es these registers. this sequence lasts approximately (6n + 30) adc cy- cles (where n is the value of the cycle count register ). drdy will be asserted at the end of the calibration. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 ..... 2 -16 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23
cs5467 ds714a1 35 advance release these values may be read and stored for future system ac offset compensation. the value is represented in two's complement notation in the range of -1.0 v acoff , i acoff < 1.0 (-1.0 v2 acoff , i2 acoff < 1.0), with the binary point to the right of the msb. 6.2.5 pulseratee register address: 15 default = 0x800000 = 1.00 (2 khz @ 4.096 mhz mclk) pulseratee sets the frequency of e1 , e2 , & e3 pulses. e1 , e2 , e3 frequency = (mclk x pulseratee) / 2048 at full scale. for a 4 khz sample rate, th e maximum pulse rate is 2 khz. the value is represented in two's comple- ment notation and in the range is -1.0 pulseratee < 1.0, with the binary point to the right of the msb. negative values have the same effect as positive. see section 5.5 energy pulse output on page 18 for more information. 6.2.6 operational mode (mode) register address: 16 default = 0x000000 e2mode e2 output mode 0 = sign of active power (default) 1 = apparent power vhpf(vhpf2) enables the high pass filter on the voltage channel. 0 = high-pass filter disabled (default) 1 = high-pass filter enabled ihpf(ihpf2) enables the high pass filter on the current channel. 0 = high-pass filter disabled (default) 1 = high-pass filter enabled e3mode1:0 e3 output mode 00 = reactive power (default) 01 = pfmon 10 = voltage sign 11 = apparent power pos positive energy only. negative energy pulses on e1 are supp ressed. however, negative p reg- ister results will no t be suppressed. afc enables automatic line frequency measurement and sets the frequency of the local sine/cosine generator used in fundamental/harmonic measurements. when afc is enabled, the epsilon register will be up dated periodically. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 23 22 21 20 19 18 17 16 ------- 15 14 13 12 11 10 9 8 --- --e2modevhpf2 76543210 ihpf2 vhpf ihpf - e3mode[1] e3mode[0] pos afc
cs5467 36 ds714a1 advance release 6.2.7 epsilon ( ) register address: 17 default = 0x01999a = 0.0125 sec epsilon ( ) is the ratio of the input line frequency to the sample frequency of the adc (see section 5.4 perform- ing measurements on page 17). epsilon is eith er written to the register, or measured during conversions. the value is represented in two's complement notation and in the range of -1.0 < 1.0, with the binary point to the right of the msb. negative values have no significance. 6.2.8 cycle count register address: 19 default = 0x000fa0 = 4000 cycle count, denoted as n, determines the length of one computation cycle . during continuous conversions, the computation cycle frequency is (mclk/k)/(1024 ? n). a one second computational cycle period occurs when mclk = 4.096 mhz, k = 1, and n = 4000. 6.2.9 reactive power (q trig , q2 trig ) registers address: 20 (q trig ), 21 (q2 trig ) the reactive power (q trig , q2 trig ) is calculated using trigonometric identities. (see section 4.3 power mea- surements on page 15). the value is represented in unsigned notation and in the range of 0 q trig < 1.0 (0 q2 trig < 1.0), with the binary point to the right of the msb. 6.2.10 temperature gain (t gain ) register address: 22 default = 0x34e2e7 = 26.443169117 temperature gain (t gain ) is utilized to convert from one temperature scale to another. the celsius scale ( o c) is the default. values will be within in the range of 0 t gain < 128. the value is represented in unsigned notation, with the binary point to the right of bit 7th msb. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 ..... 2 -11 2 -12 2 -13 2 -14 2 -15 2 -16 2 -17
cs5467 ds714a1 37 advance release 6.2.11 temperature offset (t off ) register address: 23 default = 0xf38701 = -0.0974425 temperature offset (t off ) is used to remove the temperature channel?s offset at the zero-degree reading. values are represented in two's complement notation and in the range of -1.0 t off < 1.0, with the binary point to the right of the msb. 6.2.12 temperature measurement (t meas ) register address: 26 default = 0x000000 the temperature measurement register is used to cycle -steal voltage channel 2 for temperature measurement. writing a one to the lsb causes the temperature to be measured and the temperature register (t) to be updat- ed. 6.2.13 system gain register ( sys gain ) address: 28 default = 0x500000 = 1.25 system gain (sys gain ) determines the one?s density of the cha nnel measurements. small changes in the mod- ulator due to temperature can be fine adjusted by changi ng the system gain. the value is represented in two's complement notation and in the range of -2.0 < sys gain < 2.0, with the binary point to the right of the second msb. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb -(2 1 )2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 ..... 2 -16 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22
cs5467 38 ds714a1 advance release 6.3 page 2 registers 6.3.1 voltage sag duration (vsag duration , v2sag duration ) registers address: 0 (vsag duration ), 8 (v2sag duration ) default = 0x000000 voltage sag duration (vsag duration , v2sag duration ) defines the number of instant aneous measur ements utilized to determine a sag event. setting these register to zero will disable this feature. the value is represented in un- signed notation. see section 5.6 sag and fault detect feature on page 20 6.3.2 current fault duration (isag duration , i2sag duration ) registers address: 4 (isag duration ), 12 (i2sag duration ) default = 0x000000 current fault duration (isag duration , i2sag duration ) defines the number of inst antaneous measur ements utilized to determine a sag event. setting these register to zero will disable this feature. the value is represented in un- signed notation. see section 5.6 sag and fault detect feature on page 20. 6.3.3 voltage sag level (vsag level , v2sag level ) registers address: 1 (vsag level ), 9 (v2sag level ) default = 0x000000 voltage sag level (vsag level ), v2sag level ) defines the voltage level that the magnitude of input samples, aver- aged over the sag duration, must fall below in order to register a sag condition. these value are represented in unsigned notation and in the range of 0 vsag level < 1.0 (0 v2sag level < 1.0), with the binary point to the left of the msb. see section 5.6 sag and fault detect feature on page 20. 6.3.4 current fault level (isag level , i2sag level ) registers address: 5 (isag level ), 13 (i2sag level ) default = 0x000000 current fault level (isag level , i2sag level ) defines the voltage level that the magnitude of input samples, aver- aged over the fault duration, must fall below in order to register a fault condition. these value are represented in unsigned notation and in the range of 0 isag level < 1.0 (0 i2sag level < 1.0), with the binary point to the left of the msb. see section 5.6 sag and fault detect feature on page 20. msb lsb 0 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb 0 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 ..... 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 2 -24 msb lsb 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 ..... 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 2 -24
cs5467 ds714a1 39 advance release 7. system calibration 7.1 channel offset and gain calibration the cs5467 provides digital dc offset and gain com- pensation that can be applied to the instantaneous volt- age and current measurements, and ac offset compensation to the voltage and current rms calcula- tions. since the voltage and current channels have indepen- dent offset and gain regist ers, system offset and/or gain can be performed on either channel without the calibration results from one channel affecting the oth- er. the computational flow of th e calibration sequences are illustrated in figure 13 . the flow applies to both the volt- age channel and current channel. 7.1.1 calibration sequence the cs5467 must be operating in its active state and ready to accept valid commands. refer to 5.15 com- mands on page 24. the calibration algorithms are de- pendent on the value n in the cycle count register (see figure 13 ). upon completion, the results of the calibra- tion are available in their corresponding register. the drdy bit in the status register will be set. if the drdy bit is to be output on the int pin, the drdy bit in the mask register must be set. the initial values in the ac gain and offset registers do affect the results of the cal- ibration results. 7.1.1.1 duration of calibration sequence the value of the cycle count register (n) determines the number of conversions performed by the cs5467 during a given calibration sequence. for dc offset and gain calibrations, the calibration sequence takes at least n + 30 conversion cycles to complete. for ac offset cal- ibrations, the sequence takes at least 6n + 30 adc cy- cles to complete, (about 6 computation cycles). as n is increased, the accu racy of calibration results will in- crease. 7.1.2 offset ca libration sequence for dc and ac offset calibrations, the vin (v2in ) pins of the voltage and iin (i2in ) pins of the current channels should be connected to their ground reference level. (see figure 14 .) the ac offset registers must be set to the default (0x000000). 7.1.2.1 dc offset calibration sequence channel gain should be set to 1.0 when performing dc offset calibration. initiate a dc offset calibration. the dc offset registers are updated with the negative of the av- erage of the instantaneous samples collected over a computational cycle. upon completion of the dc offset calibration the dc offset is stored in the corresponding dc offset register. the dc of fset value will be added to in modulator + x v, i, v2, i2 filter n i rms , v rms , i2 rms , v2 rms i dcoff , v dcoff , i2 dcoff , v2 dcoff i gn , v gn , i2 gn , v2 gn 0.6 + + + = names of readable/writable registers. n + x n inverse x -1 rms i acoff , v acoff , i2 acoff , v2 acoff n x -1 + gain dc offset ac offset rms instantaneous figure 13. calibration data flow + - xgain + - external connections 0v + - ain+ ain- cm + - figure 14. system calibration of offset
cs5467 40 ds714a1 advance release each instantaneous meas urement to nullify the dc component present in the system during conversion commands. 7.1.2.2 ac offset calibration sequence corresponding offset registers i acoff (i2 acoff ) and/or v acoff (v2 acoff ) should be cleared prior to initiating ac offset calibrations. initiate an ac o ffset calibration.the ac offset registers are update d with an offset value that reflects the rms output level. upon completion of the ac offset calibration the ac offset is stored in the corre- sponding ac offset register. the ac offset register val- ue is subtracted from each successive v rms and i rms calculation. 7.1.3 gain calibration sequence when performing gain calibrations, a reference signal should be applied to the vin (v2in ) pins of the volt- age and iin (i2in ) pins of the current channels that represents the desired maximum signal level. figure 15 shows the basic setup for gain calibration. for gain calibrations, there is an absolute limit on the rms voltage levels that are selected for the gain cali- bration input signals. the maximum value that the gain registers can attain is 4. ther efore, if the signal level of the applied input is low enough that it causes the cs5467 to attempt to set either gain register higher than 4, the gain calibration resu lt will be invalid and all cs5467 results obtained while performing measure- ments will be invalid. if the channel gain registers are initially set to a gain oth- er than 1.0, ac gain calibration should be used. 7.1.3.1 ac gain calibration sequence the corresponding gain register should be set to 1.0, unless a different init ial gain value is de sired. initiate an ac gain calibration. the ac gain calibration algorithm computes the rms value of the reference signal applied to the channel inputs. the rms register value is then di- vided into 0.6 and the quotient is stored in the corre- sponding gain register. each instantaneous measurement will be multiplie d by its corresponding ac gain value. a typical rms calibration va lue which allows for reason- able over-range margin would be 0.6 or 60% of the volt- age and current channel?s maximum input voltage level. two examples of ac gain calibration and the updated digital output codes of the channel?s instantaneous data registers are shown in figure 16 and 17 . figure 17 + - + - external connections in+ in- cm + - + - xgain reference signal figure 15. system calibration of gain. v rms register = 230 / 2 x 1 / 250 0.65054 250 mv 230 mv 0 v -230 mv -250 mv 0.9999... 0.92 -0.92 -1.0000... v rms register = 0.600000 250 mv 230 mv 0 v -230 mv -250 mv 0.84853 -0.84853 before ac gain calibration (vgn register = 1) after ac gain calibration (vgn register changed to approx. 0.9223) instantaneous voltage register values instantaneous voltage register values sinewave sinewave 0.92231 -0.92231 input signal input signal figure 16. example of ac gain calibration v rms register = 230 = 0.92 250 mv 230 mv 0 v -250 mv 0.9999... 0.92 -1.0000... v rms register = 0.600000 250 mv 230 mv 0 v -250 mv 0.6000 before ac gain calibration (vgain register = 1) after ac gain calibration (vgain re gister changed to approx. 0.65217) instantaneous voltage register values instantaneous voltage register values dc signal dc signal 0.65217 -0.65217 input signal input signal 250 figure 17. example of ac gain calibration
cs5467 ds714a1 41 advance release shows that a positive (or ne gative) dc-level signal can be used even though an ac gain calibration is being ex- ecuted. however, an ac signal cannot be used for dc gain cal- ibration. 7.1.3.2 dc gain calibration sequence initiate a dc gain calibration. the corresponding gain register is restored to default (1.0). the dc gain calibra- tion averages the channel?s instantaneous measure- ments over one computation cycle (n samples). the average is then divided into 1.0 and the quotient is stored in the corresponding gain register after the dc gain calibration, the instantaneous register will read at full-scale whenev er the dc leve l of the input signal is equal to the level of the dc calibration signal applied to the inputs during the dc gain calibration.the hpf option should not be enabled if dc gain calibration is utilized. 7.1.4 order of ca libration sequences 1. if the hpf option is enab led, any dc component that may be present in the selected signa l path will be re- moved and a dc offset calibration is not required. however, if the hpf option is disabled the dc offset calibration sequence should be performed. when using high-pass filter s, it is recommended that the dc offset register for the corresponding channel be set to zero. when performing dc offset calibra- tion, the corresponding gain channel should be set to one. 2. if there is an ac offset in the v rms or i rms calcula- tion, the ac offset calib ration sequence should be performed. 3. perform the gain calibration sequence. 4. finally, if an ac offset calibration was performed (step 2), the ac offset may need to be adjusted to compensate for the change in gain (step 3). this can be accomplished by restoring zero to the ac offset register and performing an ac offset calibration se- quence. the adjustment could also be done by multiplying the ac offset register value that was cal- culated in step 2 by the gain calculated in step 3 and updating the ac offset register with the product. 7.2 phase compensation the cs5467 is equipped with phase compensation to cancel out phase shifts introduced by the measurement element. phase compensation is set by bits pc[7:0] (for channel 1) in the configuration register and bits pc2[7:0] (for channel 2) in the control register the default value of pc[7:0] (pc2[7:0]) is zero. with mclk = 4.096 mhz and k = 1, the phase compensa- tion has a range of 5.4 degrees when the input signals are 60 hz. under these conditions, each step of the phase compensation register (value of one lsb) is ap- proximately 0.04 degrees. for values of mclk other than 4.096 mhz, the range and step size should be scaled by 4.096 mhz/(mclk/k). for power line fre- quencies other than 60hz, the values of the range and step size of the pc[7:0] (pc2[7:0]) bits can be deter- mined by converting the above values from angular measurement into the time domain (seconds), and then computing the new range and step size (in degrees) with respect to the new line frequency. to calculate the phase shift induced between the voltage and the current channel use the equation: 7.3 active power offset the power offset register can be used to offset system power sources that may be resident in the system, but do not originate from the power line signal. these sourc- es of extra energy in th e system contribute undesirable and false offsets to the power and energy measurement results. after determining the amount of stray power, the power offset register can be set to cancel the effects of this unwanted energy. freq = line frequency [hz] pc[7:0] = 2?s compliment number in the range of -128 < pc[7:0} < 127 phase freq 360 o pc 7:0 [] mclk k ? () 8 ? --------------------------------------------------- =
cs5467 42 ds714a1 advance release 8. auto-boot mode using e 2 prom when the cs5467 mode pin is asserted (logic 1), the cs5467 auto-boot mode is enabled. in auto-boot mode, the cs5467 downloads the required commands and register data from an external serial e 2 prom, allowing the cs5467 to begin performing energy measurements. 8.1 auto-boot configuration a typical auto-boot serial connection between the cs5467 and a e 2 prom is illustrated in figure 18 . in au- to-boot mode, the cs5467?s cs and sclk are config- ured as outputs. the cs5467 asserts cs (logic 0), provides a clock on sclk, and sends a read command to the e 2 prom on sdo. the cs5467 reads the us- er-specified commands and register data presented on the sdi pin. the e 2 prom?s programmed data is utilized by the cs5467 to change the designated registers? de- fault values and begin registering energy. figure 18 also shows the external connections that would be made to a calibrator device, such as a pc or custom calibration board. when the metering system is installed, the calibrator would be used to control calibra- tion and/or to program user-specified commands and calibration values into the e 2 prom. the user-specified commands/data will determine the cs5467?s exact op- eration, when the auto-boot initialization sequence is running. any of the valid commands can be used. 8.2 auto-boot data for e 2 prom below is an example code set for an auto-boot se- quence. this code is written into the e 2 prom by the us- er. the serial data for such a sequence is shown below in single-byte hexidecimal notation: - 7e 00 00 01 change to page 1. - 60 00 01 e0 write operation mode register, turn high-pass filters on. - 42 7f c4 a9 write value of 0x7fc4a9 to current gain register. - 46 ff b2 53 write value of 0xffb253 to voltage gain register. - 50 7f c4 a9 write value of 0x7fc4a9 to current 2 gain register. - 54 ff b2 53 write value of 0xffb253 to voltage 2 gain register. - 7e 00 00 00 change to page 0. - 74 00 00 04 unmask bit #2 (lsd) in the mask register. - e8 start continuous conversions - 78 00 01 00 write stop bit to control register, to terminate auto-boot initialization sequence. 8.3 which e 2 proms can be used? several industry-standard serial e 2 proms that will suc- cessfully run auto-boot with the cs5467 are listed be- low: ? atmel at25010, at25020 or at25040 ? national semiconductor nm25c040m8 or nm25020m8 ? xicor x25040si these types of serial e 2 proms expect a specific 8-bit command (00000011) in order to perform a memory read. the cs5467 has been hardware programmed to transmit this 8-bit command to the e 2 prom at the be- ginning of the auto-boot sequence. cs5467 eeprom e1 e2 mode sclk sdi sdo cs sck so si cs connector to calibrator vd+ 5 k 5 k pulse output counter figure 18. typical interface of e 2 prom to cs5467
cs5467 ds714a1 43 advance release 9. basic application circuits figure 19 shows the cs5467 configured to measure power in a single-phase, 3-wire system while operating in a single-supply configuration. in this diagram, a cur- rent transformer (ct) is used to sense the line current and a voltage divider is used to sense the line voltage. cs5467 r 1 r 2 13 iin1- 14 19 20 iin1+ pfmon cpuclk xout xin optional clock source serial data interface reset 2 1 cs 7 sdi 27 sdo 6 sclk 5 int 24 e1 0.1 f vrefin 12 vrefout 11 agnd dgnd 17 4 4.096 mhz r v- isolation pulse output counter 26 25 c idiff c v- c v+ c vdiff e2 iin2- iin2+ r r i- r i+ c burden idiff 1k ? 1k ? 15 16 21 28 23 vin2- vin2+ load ct r burden ct r i- r i+ 1k ? 1k ? load r 1 r 2 9 10 r v- c v- c v+ c vdiff vin1- vin1+ va+ vd+ 0.1 f 470 f 500 ? 2uf 500 l2 10 ? 3 0.1 f 10 k ? 5k ? l1 18 n figure 19. typical connection diagram (single-phase, 3-wire ? direct connect to power line)
cs5467 44 ds714a1 advance release 10.package dimensions notes: 3. ?d? and ?e1? are reference datums and do not included mo ld flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flas h or protrusions shall not exceed 0.20 mm per side. 4. dimension ?b? does not include dambar protrusion/intru sion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximum mate rial condition. dambar intrusion shall not reduce dimension ?b? by more than 0.07 mm at least material condition. 5. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a -- -- 0.084 -- -- 2.13 a1 0.002 0.006 0.010 0.05 0.13 0.25 a2 0.064 0.068 0.074 1.62 1.73 1.88 b 0.009 -- 0.015 0.22 -- 0.38 2,3 d??????1 e 0.291 0.307 0.323 7.40 7.80 8.20 e1 0.197 0.209 0.220 5.00 5.30 5.60 1 e 0.022 0.026 0.030 0.55 0.65 0.75 l 0.025 0.03 0.041 0.63 0.75 1.03 0 4 8 0 4 8 jedec #: mo-150 controlling dimensio n is millimeters. e n 12 3 e b 2 a1 a2 a d se ati ng plane e1 1 l side view end v iew top view 28l ssop package drawing
cs5467 ds714a1 45 advance release 11. ordering information 12. environmental, manufac turing, & handling information * msl (moisture sensitivity level) as specified by ipc/jedec j-std-020. model temperature package cs5467-is -40 to +85 c 28-pin ssop CS5467-ISZ (lead free) model number peak reflow temp msl rating* max floor life cs5467-is 240 c 2 365 days CS5467-ISZ (lead free) 260 c 3 7 days
cs5467 46 ds714a1 advance release 13. revision history revision date changes a1 mar 2006 advance release contacting cirrus logic support for all product questions and inquiries cont act a cirrus logic sa les representative. to find the one nearest to you go to www.cirrus.com important notice ?advance? product information describes products that are in development and subject to development changes. cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual proper ty rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general di stribution, advertising or promotional purposes, or for creating any work for resale. certain applications usin g semiconductor products may involve potential risks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus products are not desi gned, authorized or warranted for use in aircraft systems, military applications, products s urgically implanted into the body, automotive safety or security de- vices, life support products or other critical applic ations. inclusion of cirrus products in such applications is understood to be fully at the customer's risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantab ility and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or cu stomer's customer uses or permits the use of cirrus products in critical applica- tions, customer agrees , by such use, to fully indemnify cirrus, its officers, di rectors, employees, distributors and other agents from any and all liability, including attorneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. spi is a trademark of motorola, inc. microwire is a trademark of national semiconductor corporation.

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